1. Technical Field
The present disclosure relates to a method for manufacturing electronic devices integrated on a semiconductor substrate and corresponding devices, and to a method for manufacturing a power MOS transistor of the vertical type on a semiconductor substrate with wide band gap comprising a superficial semiconductor layer with wide band gap.
The disclosure also relates to a power MOSFET device integrated on a wide band gap semiconductor substrate, and to vertical high voltage power MOS transistors of the multi-drain type and the following description is made with reference to this field of application by way of illustration only.
2. Description of the Related Art
As is well known, silicon carbide (SiC) is a wide band gap semiconductor material, i.e., with an energetic value Eg of the band gap higher than 1.1 eV, with such physical characteristics as to make it ideal for the formation of electronic switches for power applications. In the following table some physical parameters are reported of the most common silicon carbide polytypes, in comparison with silicon (Si).
Si3C-SiC6H-SiC4H-SiCEg (eV)1.12.333.3Vsn1 × 1072.5 × 1072 × 1072 × 107μn (cm2/Vs)13501000380 947εr11.89.66 9.79.7Ec (V/cm)2 × 105  3 × 1064 × 1063 × 106K (W/cm K)1.54.955where Eg is the energetic value of the band gap, Vsn is the saturation speed of the electrons, μn is the mobility of the electrons, ∈r is the dielectric constant, Ec is the critical electric field, and k is the thermal conductivity.
From the parameters reported in such table, it is possible to deduce that power electronic devices formed on silicon carbide substrates as compared to power electronic devices formed on silicon substrates exhibit the following advantageous characteristics:                a low output resistance in conduction being the breakdown voltage equal (due to the high critical electric field value Ec);        a low leakage current (due to the high band gap energetic value, Eg),        high working temperature and high working frequencies (due to the high thermal conductivity k and saturation speed Vns values).        
It is to be noted that due to the high value of the critical electric field Ec in silicon carbide semiconductor substrates with respect to silicon semiconductor substrates, it is possible to form power devices integrated on silicon carbide semiconductor substrates that can withstand high cut-off voltages with a very reduced epitaxial thickness.
For example, with reference to FIG. 1, a multi-drain MOS power device 3 of the known type is described which comprises a heavily doped silicon semiconductor substrate 1 of the N+ type, whereon a semiconductor epitaxial layer 2 is formed of the same N type.
The epitaxial layer 2 forms a common drain layer for a plurality of elementary units forming the MOS power device 3. Each elementary unit comprises a body region 4 of the P type formed in the epitaxial layer 2.
In the epitaxial layer 2, below each body region 4, there is a column region 5 of the P type which extends downwards for the whole thickness of the epitaxial layer 2 towards the semiconductor substrate 1.
In particular, each column region 5 is aligned and in contact with a respective body region 4.
The MOS power device 3 also exhibits, outside the body regions 4, heavily doped source regions 6 of the N type.
The surface of the epitaxial layer 2 is thus covered with a thin gate oxide layer 7 and with a polysilicon layer 8. Openings are thus provided in the polysilicon layer 8 and in the thin gate oxide layer 7 to uncover the surface of the epitaxial layer 2 in correspondence with each source region 6. An insulating layer 9 completely covers the polysilicon layer 8 and it partially covers the source regions 6, so as to enable a source metallic layer 1A to contact the source regions 6 and the body regions 4. A drain metallic layer 1B is also provided on the lower substrate of the semiconductor substrate 1.
To form a device 3 able to withstand a breakdown voltage BV equal to 600 V, a drain epitaxial layer 2 is to be provided formed in silicon and with a thickness equal to 60 mm and concentration equal to 2×1014 at/cm3. If the drain epitaxial layer 2 is instead formed in silicon carbide, it can have a thickness of only 4 mm and concentration equal to 1×1016 at/cm3, thus obtaining a much more compact device 3.
Moreover in these devices 3 of the multi-drain type, the presence thus of the column regions 5 allows to reduce the resistivity of the epitaxial layer 2 without decreasing the breakdown voltage BV of the device 3. With this type of device 3 it is thus possible to reach a predetermined breakdown voltage BV with a resistivity of the epitaxial layer 2 lower than that used in conventional MOSFET devices, and, in consequence, to obtain power MOSFET transistors with reduced output resistance Ron.
As shown in FIGS. 2 and 3 the electric field E in the column region 5 of type and along the drain epitaxial layer 2 the electric field Ec is substantially constant. In particular, it verifies that the electric field E inside the device 3 exhibits the trend shown in FIG. 2, with reference to line II-II of FIG. 1. It thus results that the electric field trend is constant and equal to the critical electric field value in correspondence with a longitudinal dimension of the column region 5 (points A and C of FIGS. 1 and 2).
Similarly it is verified that such critical electric field Ec trend is constant and equal to the critical electric field value in correspondence with line III-III of FIG. 1, i.e., in correspondence with a transversal dimension of the device 3, both of the column regions 5, and in the drain epitaxial layer 2, this allows to obtain, being the drain layer thickness identical, a much higher breakdown voltage BV with respect to a MOS device not exhibiting the column region 5.
Moreover, it is known that the output resistance Ron is proportional to the resistivity ρepi and to the thickness thepi of the epitaxial layer 2 while it is inversely proportional to the conduction area Acond, which, for multi-drain transistors, is equal to the active area of the device 3 decreased of the area occupied by the column regions 5.
These three parameters, and in particular the resistivity ρepi, in multi-drain devices 3 are lower with respect to those of conventional power devices. Therefore, the output resistance Ron of these devices 3 of the multi-drain type is lower than that of conventional power devices.
Moreover, it is well known that for forming any electronic device integrated on a silicon carbide substrate it is necessary to introduce dopant elements which produce, inside the lattice matrix of the silicon carbide substrate, doped regions of the N or P type.
In particular, nitrogen (N) and phosphorus (P) introduce donors into the lattice matrix forming doped regions of the N type, boron (B) and aluminum (Al) introduce acceptors and form doped regions of the P type.
A particularly important technological problem linked to the formation of such doped regions is that any type of dopant implanted into a silicon carbide substrate has negligible diffusion coefficient D up to temperatures in the order of 1800° C. as described in the article “Properties of Silicon Carbide” by Gary L. Harris.
In particular, at such high temperatures, nitrogen has a diffusion coefficient D in the silicon carbide equal to 5×10−12 cm2 s−1, oxygen has a diffusion coefficient D equal to 1.5×10−16 cm2s−1, while boron has a diffusion coefficient D equal to 2.5×10−13 cm2s−1.
In silicon, boron has a diffusion coefficient D equal to 2.5×10−13 cm2s−1 at a temperature of about 1150° C. and thus it approximately has the same diffusion with respect to a silicon carbide substrate at a much lower temperature.
The diffusion of dopant species used for forming the doped regions necessary for the formation of power electronic devices is thus a problematic technical factor in case silicon carbide substrates are used.
Finally, analyses carried out by the Applicant have highlighted that the range projected by the boron into the silicon carbide, i.e., the typical distance covered by the boron inside the silicon carbide for a determined implantation energy, increases almost linearly with the implant energy, as shown in FIG. 4.
The technical problem underlying the present disclosure is that of devising a method for forming a power device integrated on a silicon carbide semiconductor substrate, having such structural characteristics as to allow to obtain electronic devices with very contained dimensions and exhibiting a very low output voltage, overcoming the limits and the drawback still affecting the devices formed according to known methods.